1. Field of the Invention
The invention generally relates to system testing and in particular to a method and apparatus for identifying faulty gates within an integrated circuit.
2. Description of Related Art
It is often necessary to identify and locate faults occurring within a digital system such as an integrated circuit. The identification of faults within a digital system, herein refer to as fault diagnosis, is commonly employed during design debug, manufacturing tests, failure analysis, and depot repair. Typically, fault diagnosis is performed by applying a known stimulus to the input of the system, then comparing an observed output response with a predetermined expected response. Any mismatch between the observed and expected response may be an indication of a failure within the system. If such a mismatch occurs, it is desirable to identify the faulty elements of the system which are responsible for the mismatch between the observed and the expected response.
Conventional techniques for generating test stimulus will now be described, then techniques for correlating mismatches between observed and expected stimulus responses with candidate faulty system elements will be discussed.
One standard method for generating and processing test stimulus is an industry standard chip testing protocol known as JTAG and internal scan. The JTAG protocol, sponsored by the IEEE, defines a 5-pin serial interface to a VLSI chip that allows certain operations to be performed on the chip outside of normal operations.
An example of a test employing the JTAG protocol is as follows. An input vector (defined by a series of one's (1's) and zeros (0's) equal in length to the total number of flip flops and latches in an internal scan chain in the integrated circuit under test) is shifted into the integrated circuit through a JTAG input port. The input vector defines the internal state of the integrated circuit. Next, the circuit is switched from a test mode to a normal operating mode and run for one clock cycle. At the end of the cycle, many of the internal flip flops and latches are updated with new values due to normal operations of the integrated circuit. The integrated circuit is then switched back to the test mode and the values of the flip flops and latches are shifted out through the JTAG port. The bits of the test vectors shifted out are compared against a previously determined expected value and, if any mismatches occur, the circuit is thereby identified as being non-functional.
In this manner, the JTAG protocol allows one to determine whether an integrated circuit is functional or non-functional. However, as noted above, it is often desirable to further identify the source of the non-functionality, i.e., to identify actual faulty gates such as faulty flip flops, latches etc.
A number of techniques have been developed for performing fault diagnosis to identify faulty gates responsible for a mismatch between observed and expected test vector outputs. One such technique, a "union" method, provides, for each respective bit of the output test vector, a list of all gates which may be responsible for any mismatch of the respective bit.
FIG. 1 illustrates the union method of fault diagnosis. In FIG. 1, three fault sets 10,12 and 14 are illustrated. Each set of faults represents all candidate faults associated with a mismatched bit of a test vector. For example, if a test vector includes one hundred bits and the 14th, 32nd and 87th bits of the output test vector do not match corresponding bits of an expected test vector, then sets 10, 12 and 14 may respectively denote all faults which could be responsible for the mismatched bits. Within FIG. 1, a U is illustrated within each portion of each set indicating the union.
A list of candidate faulty gates is generated based on all mismatched bits within a test vector or within sets of test vectors. A candidate faulty gate is a gate which may be responsible for a fault in the system but which has not yet been determined to be actually faulty. However, the number of faulty gates identified may be prohibitively large. For example, to adequately test a complex integrated circuit having thousands of gates, a large number of test vectors may be required, each having hundreds or thousands of individual bits. A comprehensive list of all gates associated with all mismatched bits within all test vectors may be prohibitively large and may, in fact, include each and every gate within the integrated circuit.
Accordingly, alternative techniques have been developed for refining the comprehensive union-based list to achieve a shorter list providing for more likely faulty gate candidates. In one such alternative technique, the "intersection" method, only faulty gates which are associated with every mismatched bit of every test vector are selected. The intersection method is effective in narrowing the list of candidate faulty gates to those which are more likely to represent the actual fault. However, the intersection method yields a null list when there are no faults in common with all the mismatch bits of all of the test vectors.
FIG. 2 illustrates the intersection method of fault diagnosis. In FIG. 2, the same three sets of candidate faults, 10,12 and 14 are illustrated. The intersection of fault sets 10,12 and 14 is labeled I and denoted by reference numeral 16. Only those faults within the intersecting region are identified as being candidate faults. Other candidate faults which are not common to all three fault sets are not selected. The intersection method would not identify the actual fault if it is one of lesser likelihood. Furthermore, as noted above, in circumstances where there are no faults common to all fault sets, then the intersection method yields only a null set and thereby provides no useful information regarding the identification of the actual fault
As can be appreciated, practical fault diagnosis is difficult or impossible if the resulting list of candidate faults either encompasses each and every gate within the integrated circuit or includes no gates whatsoever. It would be desirable to provide an improved method and apparatus for performing fault diagnosis which has a greater likelihood of yielding a useful list of candidate faults than can be achieved with the conventional union or intersection methods. In particular, it would be desirable to provide a method of fault diagnosis which produces a small, but non-null, list of likely faults. Certain aspects of the present invention are drawn to such an improved method.
Another possible drawback with conventional fault diagnosis procedures is that it is often difficult to locate the actual gates within the integrated circuit which correspond to the candidate faulty gates provided by the fault diagnosis. To determine whether any particular gate may be faulty, it is often necessary to visually observe the gate, perhaps using a microscope or similar magnifying device, to determine if a physical defect has occurred within the gate. To observe the actual gate, it is first necessary to determine the physical location within the die or chip containing integrated circuit. Heretofore, no effective tool has been developed for correlating a list of candidate faulty gates produced by fault diagnosis with the actual locations within a die containing integrated circuits. Rather, test personnel are typically required to compare the list of candidate faulty gates with circuit schematics illustrating the integrated circuit to determine the location of the faults. Typically, only those engineers who are highly familiar with the design of the particular integrated circuit being tested are capable of determining the physical location of gates based upon a faulty gate list and such an analysis is usually time-consuming. Furthermore, it is often difficult to find engineers who are highly familiar with the design of the integrated circuit, particularly a year or more after the design has been completed.
Accordingly, it would be desirable to provide a more efficient method for identifying the physical location of a candidate faulty gate within an integrated circuit based on faulty gate candidates developed during a JTAG, or similar, test. It is to that end that a second aspect of the present invention is drawn.